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-- Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 11.4
--  \   \         Application : sch2hdl
--  /   /         Filename : top.vhf
-- /___/   /\     Timestamp : 05/05/2010 13:02:14
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: sch2hdl -sympath C:/Users/Tom/Documents/lcpd-scope/vhdl/project/ipcore_dir -intstyle ise -family spartan3 -flat -suppress -vhdl C:/Users/Tom/Documents/lcpd-scope/vhdl/project/top.vhf -w C:/Users/Tom/Documents/lcpd-scope/vhdl/project/top.sch
--Design Name: top
--Device: spartan3
--Purpose:
--    This vhdl netlist is translated from an ECS schematic. It can be 
--    synthesized and simulated, but it should not be modified. 
--

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity top is
   port ( AD_DB       : in    std_logic_vector (7 downto 0); 
          AD_INT      : in    std_logic; 
          PCI_CBE     : in    std_logic_vector (3 downto 0); 
          PCI_CLK     : in    std_logic; 
          PCI_IDSEL   : in    std_logic; 
          PCI_nFRAME  : in    std_logic; 
          PCI_nIRDY   : in    std_logic; 
          PCI_nRES    : in    std_logic; 
          SPI_MISO    : in    std_logic; 
          AD_WR       : out   std_logic; 
          PCI_nDEVSEL : out   std_logic; 
          PCI_nINT    : out   std_logic; 
          PCI_nPERR   : out   std_logic; 
          PCI_nSERR   : out   std_logic; 
          PCI_nSTOP   : out   std_logic; 
          PCI_nTRDY   : out   std_logic; 
          PCI_PAR     : out   std_logic; 
          SPI_CLK     : out   std_logic; 
          SPI_CS      : out   std_logic; 
          SPI_MOSI    : out   std_logic; 
          PCI_AD      : inout std_logic_vector (31 downto 0));
end top;

architecture BEHAVIORAL of top is
   attribute BOX_TYPE   : string ;
   signal XLXN_110                   : std_logic;
   signal XLXN_196                   : std_logic_vector (24 downto 0);
   signal XLXN_197                   : std_logic_vector (11 downto 0);
   signal XLXN_200                   : std_logic_vector (31 downto 0);
   signal XLXN_201                   : std_logic_vector (1 downto 0);
   signal XLXN_202                   : std_logic_vector (7 downto 0);
   signal XLXN_203                   : std_logic_vector (7 downto 0);
   signal XLXN_205                   : std_logic_vector (31 downto 0);
   signal XLXN_208                   : std_logic_vector (31 downto 0);
   signal XLXN_212                   : std_logic_vector (1 downto 0);
   signal XLXN_213                   : std_logic;
   signal XLXN_214                   : std_logic;
   signal XLXN_218                   : std_logic_vector (31 downto 0);
   signal XLXN_220                   : std_logic_vector (0 downto 0);
   signal XLXN_227                   : std_logic;
   signal XLXN_231                   : std_logic;
   signal XLXN_234                   : std_logic;
   signal XLXN_235                   : std_logic;
   signal XLXN_238                   : std_logic;
   signal XLXN_242                   : std_logic;
   signal XLXN_244                   : std_logic_vector (31 downto 0);
   signal XLXN_247                   : std_logic_vector (31 downto 0);
   signal XLXN_249                   : std_logic_vector (11 downto 0);
   signal XLXN_252                   : std_logic_vector (0 downto 0);
   signal XLXN_253                   : std_logic;
   signal XLXN_254                   : std_logic;
   signal XLXN_256                   : std_logic;
   signal XLXN_257                   : std_logic;
   signal XLXN_268                   : std_logic;
   signal XLXN_271                   : std_logic;
   signal XLXN_274                   : std_logic;
   signal XLXI_1_wb_err_i_openSignal : std_logic;
   signal XLXI_1_wb_rty_i_openSignal : std_logic;
   signal XLXI_44_ack_4_openSignal   : std_logic;
   signal XLXI_44_data_4_openSignal  : std_logic_vector (31 downto 0);
   signal XLXI_44_ena_4_openSignal   : std_logic;
   signal XLXI_52_gpio_i_openSignal  : std_logic;
   component pci32tLite
      port ( clk33    : in    std_logic; 
             rst      : in    std_logic; 
             frame    : in    std_logic; 
             irdy     : in    std_logic; 
             idsel    : in    std_logic; 
             wb_ack_i : in    std_logic; 
             wb_rty_i : in    std_logic; 
             wb_err_i : in    std_logic; 
             wb_int_i : in    std_logic; 
             cbe      : in    std_logic_vector (3 downto 0); 
             wb_dat_i : in    std_logic_vector (31 downto 0); 
             par      : out   std_logic; 
             trdy     : out   std_logic; 
             devsel   : out   std_logic; 
             stop     : out   std_logic; 
             perr     : out   std_logic; 
             serr     : out   std_logic; 
             intb     : out   std_logic; 
             wb_we_o  : out   std_logic; 
             wb_stb_o : out   std_logic; 
             wb_cyc_o : out   std_logic; 
             wb_adr_o : out   std_logic_vector (24 downto 0); 
             wb_dat_o : out   std_logic_vector (31 downto 0); 
             wb_sel_o : out   std_logic_vector (3 downto 0); 
             ad       : inout std_logic_vector (31 downto 0));
   end component;
   
   component INV
      port ( I : in    std_logic; 
             O : out   std_logic);
   end component;
   attribute BOX_TYPE of INV : component is "BLACK_BOX";
   
   component Dual_Port_Ram
      port ( clka  : in    std_logic; 
             ena   : in    std_logic; 
             clkb  : in    std_logic; 
             enb   : in    std_logic; 
             wea   : in    std_logic_vector (0 downto 0); 
             addra : in    std_logic_vector (11 downto 0); 
             dina  : in    std_logic_vector (31 downto 0); 
             web   : in    std_logic_vector (0 downto 0); 
             addrb : in    std_logic_vector (11 downto 0); 
             dinb  : in    std_logic_vector (31 downto 0); 
             douta : out   std_logic_vector (31 downto 0); 
             doutb : out   std_logic_vector (31 downto 0));
   end component;
   
   component adr_decoder
      port ( wb_adr_i   : in    std_logic_vector (24 downto 0); 
             ram_ena_o  : out   std_logic; 
             spi_ena_o  : out   std_logic; 
             gpio_ena_o : out   std_logic; 
             ram_adr_o  : out   std_logic_vector (11 downto 0); 
             spi_adr_o  : out   std_logic_vector (1 downto 0); 
             gpio_adr_o : out   std_logic_vector (1 downto 0));
   end component;
   
   component ad8020_interface
      port ( INT     : in    std_logic; 
             clk_i   : in    std_logic; 
             start_i : in    std_logic; 
             DB      : in    std_logic_vector (7 downto 0); 
             WR      : out   std_logic; 
             ena_o   : out   std_logic; 
             we_o    : out   std_logic; 
             clk_o   : out   std_logic; 
             int_out : out   std_logic; 
             adr_o   : out   std_logic_vector (11 downto 0); 
             data_o  : out   std_logic_vector (31 downto 0); 
             state_o : out   std_logic_vector (2 downto 0));
   end component;
   
   component data_out_mux
      port ( ena_1     : in    std_logic; 
             ena_2     : in    std_logic; 
             ena_3     : in    std_logic; 
             ena_4     : in    std_logic; 
             ack_1     : in    std_logic; 
             ack_2     : in    std_logic; 
             ack_3     : in    std_logic; 
             ack_4     : in    std_logic; 
             data_1    : in    std_logic_vector (31 downto 0); 
             data_2    : in    std_logic_vector (31 downto 0); 
             data_3    : in    std_logic_vector (31 downto 0); 
             data_4    : in    std_logic_vector (31 downto 0); 
             wb_ack_o  : out   std_logic; 
             wb_data_o : out   std_logic_vector (31 downto 0));
   end component;
   
   component simple_spi_top
      port ( clk_i  : in    std_logic; 
             rst_i  : in    std_logic; 
             cyc_i  : in    std_logic; 
             stb_i  : in    std_logic; 
             we_i   : in    std_logic; 
             miso_i : in    std_logic; 
             adr_i  : in    std_logic_vector (1 downto 0); 
             dat_i  : in    std_logic_vector (7 downto 0); 
             ack_o  : out   std_logic; 
             inta_o : out   std_logic; 
             sck_o  : out   std_logic; 
             mosi_o : out   std_logic; 
             dat_o  : out   std_logic_vector (7 downto 0));
   end component;
   
   component bus_convert_8_32
      port ( data_8  : in    std_logic_vector (7 downto 0); 
             data_32 : out   std_logic_vector (31 downto 0));
   end component;
   
   component bus_convert_32_8
      port ( data_32 : in    std_logic_vector (31 downto 0); 
             data_8  : out   std_logic_vector (7 downto 0));
   end component;
   
   component GPIO_Module
      port ( wb_clk    : in    std_logic; 
             wb_stb    : in    std_logic; 
             wb_cyc    : in    std_logic; 
             gpio_i    : in    std_logic; 
             wb_we     : in    std_logic; 
             wb_data_i : in    std_logic_vector (31 downto 0); 
             wb_adr_i  : in    std_logic_vector (1 downto 0); 
             wb_ack    : out   std_logic; 
             gpio_o_1  : out   std_logic; 
             gpio_o_2  : out   std_logic; 
             gpio_o_3  : out   std_logic; 
             gpio_o_4  : out   std_logic; 
             wb_data_o : out   std_logic_vector (31 downto 0));
   end component;
   
   component AND2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND2 : component is "BLACK_BOX";
   
   component ad8020_clk_divider
      port ( clk_in  : in    std_logic; 
             clk_out : out   std_logic);
   end component;
   
begin
   XLXI_1 : pci32tLite
      port map (cbe(3 downto 0)=>PCI_CBE(3 downto 0),
                clk33=>PCI_CLK,
                frame=>PCI_nFRAME,
                idsel=>PCI_IDSEL,
                irdy=>PCI_nIRDY,
                rst=>XLXN_110,
                wb_ack_i=>XLXN_242,
                wb_dat_i(31 downto 0)=>XLXN_244(31 downto 0),
                wb_err_i=>XLXI_1_wb_err_i_openSignal,
                wb_int_i=>XLXN_256,
                wb_rty_i=>XLXI_1_wb_rty_i_openSignal,
                devsel=>PCI_nDEVSEL,
                intb=>PCI_nINT,
                par=>PCI_PAR,
                perr=>PCI_nPERR,
                serr=>PCI_nSERR,
                stop=>PCI_nSTOP,
                trdy=>PCI_nTRDY,
                wb_adr_o(24 downto 0)=>XLXN_196(24 downto 0),
                wb_cyc_o=>XLXN_238,
                wb_dat_o(31 downto 0)=>XLXN_208(31 downto 0),
                wb_sel_o=>open,
                wb_stb_o=>XLXN_268,
                wb_we_o=>XLXN_274,
                ad(31 downto 0)=>PCI_AD(31 downto 0));
   
   XLXI_3 : INV
      port map (I=>PCI_nRES,
                O=>XLXN_110);
   
   XLXI_40 : Dual_Port_Ram
      port map (addra(11 downto 0)=>XLXN_197(11 downto 0),
                addrb(11 downto 0)=>XLXN_249(11 downto 0),
                clka=>PCI_CLK,
                clkb=>XLXN_254,
                dina(31 downto 0)=>XLXN_208(31 downto 0),
                dinb(31 downto 0)=>XLXN_247(31 downto 0),
                ena=>XLXN_213,
                enb=>XLXN_253,
                wea(0)=>XLXN_220(0),
                web(0)=>XLXN_252(0),
                douta(31 downto 0)=>XLXN_200(31 downto 0),
                doutb=>open);
   
   XLXI_42 : adr_decoder
      port map (wb_adr_i(24 downto 0)=>XLXN_196(24 downto 0),
                gpio_adr_o(1 downto 0)=>XLXN_212(1 downto 0),
                gpio_ena_o=>XLXN_271,
                ram_adr_o(11 downto 0)=>XLXN_197(11 downto 0),
                ram_ena_o=>XLXN_213,
                spi_adr_o(1 downto 0)=>XLXN_201(1 downto 0),
                spi_ena_o=>XLXN_214);
   
   XLXI_43 : ad8020_interface
      port map (clk_i=>XLXN_254,
                DB(7 downto 0)=>AD_DB(7 downto 0),
                INT=>AD_INT,
                start_i=>XLXN_257,
                adr_o(11 downto 0)=>XLXN_249(11 downto 0),
                clk_o=>open,
                data_o(31 downto 0)=>XLXN_247(31 downto 0),
                ena_o=>XLXN_253,
                int_out=>XLXN_256,
                state_o=>open,
                we_o=>XLXN_252(0),
                WR=>AD_WR);
   
   XLXI_44 : data_out_mux
      port map (ack_1=>XLXN_268,
                ack_2=>XLXN_235,
                ack_3=>XLXN_234,
                ack_4=>XLXI_44_ack_4_openSignal,
                data_1(31 downto 0)=>XLXN_200(31 downto 0),
                data_2(31 downto 0)=>XLXN_205(31 downto 0),
                data_3(31 downto 0)=>XLXN_218(31 downto 0),
                data_4(31 downto 0)=>XLXI_44_data_4_openSignal(31 downto 0),
                ena_1=>XLXN_213,
                ena_2=>XLXN_214,
                ena_3=>XLXN_271,
                ena_4=>XLXI_44_ena_4_openSignal,
                wb_ack_o=>XLXN_242,
                wb_data_o(31 downto 0)=>XLXN_244(31 downto 0));
   
   XLXI_46 : simple_spi_top
      port map (adr_i(1 downto 0)=>XLXN_201(1 downto 0),
                clk_i=>PCI_CLK,
                cyc_i=>XLXN_238,
                dat_i(7 downto 0)=>XLXN_202(7 downto 0),
                miso_i=>SPI_MISO,
                rst_i=>PCI_nRES,
                stb_i=>XLXN_227,
                we_i=>XLXN_274,
                ack_o=>XLXN_235,
                dat_o(7 downto 0)=>XLXN_203(7 downto 0),
                inta_o=>open,
                mosi_o=>SPI_MOSI,
                sck_o=>SPI_CLK);
   
   XLXI_49 : bus_convert_8_32
      port map (data_8(7 downto 0)=>XLXN_203(7 downto 0),
                data_32(31 downto 0)=>XLXN_205(31 downto 0));
   
   XLXI_51 : bus_convert_32_8
      port map (data_32(31 downto 0)=>XLXN_208(31 downto 0),
                data_8(7 downto 0)=>XLXN_202(7 downto 0));
   
   XLXI_52 : GPIO_Module
      port map (gpio_i=>XLXI_52_gpio_i_openSignal,
                wb_adr_i(1 downto 0)=>XLXN_212(1 downto 0),
                wb_clk=>PCI_CLK,
                wb_cyc=>XLXN_238,
                wb_data_i(31 downto 0)=>XLXN_208(31 downto 0),
                wb_stb=>XLXN_231,
                wb_we=>XLXN_274,
                gpio_o_1=>XLXN_257,
                gpio_o_2=>SPI_CS,
                gpio_o_3=>open,
                gpio_o_4=>open,
                wb_ack=>XLXN_234,
                wb_data_o(31 downto 0)=>XLXN_218(31 downto 0));
   
   XLXI_53 : AND2
      port map (I0=>XLXN_268,
                I1=>XLXN_274,
                O=>XLXN_220(0));
   
   XLXI_54 : AND2
      port map (I0=>XLXN_268,
                I1=>XLXN_214,
                O=>XLXN_227);
   
   XLXI_55 : AND2
      port map (I0=>XLXN_268,
                I1=>XLXN_271,
                O=>XLXN_231);
   
   XLXI_56 : ad8020_clk_divider
      port map (clk_in=>PCI_CLK,
                clk_out=>XLXN_254);
   
end BEHAVIORAL;


